MSI MS-6852 Uživatelský manuál

AN-764 Application Note A FLOPPY DISK CONTROLLER USING THE MC6852 SSDA AND OTHER M6800 MICROPROCESSOR FAMILY PARTS Prepared by: Larry A. Parker Semico

SSDA PREPARATION FOR READ Table 2 summarizes the necessary sequence of SSDA register programming steps for a read operation. A further explanat

TABLE 2 -SSOA PREPARATION FOR READ Register Data Function & Step Address R/W 07 06 05 04 03 02 01 DO Comments 1 SSDACR Rx Rs Tx Rs Strip Clear

logic. The switch clock rate flip-flop's outputs also control the selection of 2X write data and clock or IX write data and clock being fed to

FIGURE 9-Write Synchronization Simplified Circuit Diagram SSDA MC6852 TxD Write Osc B 500 kHz TUF TxC A Ie I 1 ( N Sit Cou nter 0 Wrt Data C 00 Wrt

FIGURE 11-Write Switch Clock Rate Timing Diagram A Write Osc -500 kHz B c D E F H SSOA -TxO I· 5 'I· 7 ' F (Track No. 64) F E ---I 1 J..l

Write Osc 500 kHz K PIA -+Shift CRCC A D K E p s c H F B J A FIGURE 13-Write CRCC Simplified Block Diagram SSDA MC6852 TxD B TUF I C ( ~ Bit Counter D

A K D c E F H N FIGURE 15-Write CRCC Detailed Timing A Write Osc r-2 MS--i ~ Clocked +Shift CRc~r-I-.!..I-------~r------I ---I J1 MS max (tTDD) ~ r-1

MOTOROLA Seft"liconduci:or Produci:s Inc. BOX 20912 • PHOENIX, ARrZONA 85036 • A SUBSIDIARY OF MOTOROLA INC. 10692 PRINTED IN USA 1O~76 IMPERIAl

A FLOPPY DISK CONTROLLER USING THE MC6852 SSDA AND OTHER M6800 MICROPROCESSOR FAMILY PARTS INTRODUCTION With the introduction of the MC6852 SSDA, t

Timer on 1/0 Module DC-OF FIGURE 1 -M6800 Floppy Disc Controller Schematic i;I DRIVE INTERFACE ~ ~ N '" > > j ~ j ! ! ~ ~ .l! cr ., I

To MPU System U IV ~ -IV 2 .., c 0 (J "0 '" C '" .., '" '" 0 '" ~ :J "0 Cl. "0 :2 <

written with fewer than 600 bytes of code. Operating systems suitable to most user needs can be done within two to four kilobytes. Spec

+5 + -Disk Data FIGURE 3-Data Recovery Circuit 7416119316 P3 C V P2 F req/Phase Filter VCO -r--1 k Detector P1 V~PU -R fa PU 5V = PO F = ,---CET ~ CE

Raw Disk Data (Serial) Reset PIA PBO Data Recovery Clock FIGURE 5-Read Data Simplified Logic Diagram SSDA (MC6852) Data~----------------------------

The clock and data bit pattern used for sync match with the IBM 3740 format is a hex F5. The example in Figure 6·B shows the ID address mar

FIGURE 7-CRC Read Error Check-Simplified Circuit Diagram G B a-Bit CRC Data Data D Shift a Rd D Data C Recovery CRC MC8506 CRC Clock Rd C Clock E En